Integrated circuit memory devices are widely used in consumer and commercial applications. As is well known to those having skill in the art, one type of integrated circuit memory device is a Dynamic Random Access Memory (DRAM). In a DRAM, data is stored as charge on a capacitor. Since the charge dissipates over time, a conventional refresh operation is periodically performed to retain the stored data.
As is also known to those having skill in the art, a semiconductor memory device may be divided into a cell area, in which memory cells are formed, and a peripheral area. In the cell area, memory cells composed of transistors arranged in an array and capacitors coupled to the transistors are formed. Transistors having different functions are formed in the peripheral area including a column decoder and a row decoder that control the input and output of information to and from the memory cells in the cell area.
As the integration density of semiconductor memory devices continues to increase, the reduced size of transistors may reduce operational voltages. This may impact the refreshing characteristics of memory cells. Historically, cell transistors of the memory cells are generally maintained at a voltage of 0V in an unapplied voltage state. However, it has been found that application of a negative bias to the cell transistors may be efficient for refreshing, so that the cell transistors are kept at a negative level to reduce an off state current of unselected cell transistors. Accordingly, it is known to include additional gate negative-bias transistors, also referred to herein as refresh transistors, in the peripheral area.
As shown in FIG. 8, since the gate negative-bias transistors are formed in a peripheral area P adjacent to the cell area C, the gate negative-bias transistors may be affected by the memory cells in the cell area C during a manufacturing process. The design and operation of a conventional semiconductor memory device of FIG. 8 is well known to those having skill in the art and need not be described further herein.
Memory cells generally include insulated gate field effect transistors, conventionally referred to as MOS transistors, that are highly integrated in a matrix form to occupy relatively small areas. MOS transistors, which occupy relatively large areas, are formed in the peripheral areas. Since the MOS transistors that apply negative biases to gates of cell transistors are connected to back bias voltages VBB2 in an off state, they may need to be adjusted to a high threshold voltage Vt.